| ISBN: ISSN: 0278-0070
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| ISBN: DOI: 10.1109/43.703833
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| |
| description |
Implementing a built-in self-test by a "test per clock"
scheme offers advantages concerning fault coverage, detection of
delay faults and test application time. Such a scheme is implemented
by test registers, for instance BILBOs or CBILBOs, which are
inserted into the circuit structure at appropriate places. An
algorithm is presented which is able to find the cost optimal
placement of test registers for nearly all the ISCAS'89
sequential benchmark circuits, and a suboptimal solution with
slightly higher costs is obtained for all the circuits within a few
minutes of computing time. The algorithm can also be applied to the
Minimum Feedback Vertex Set problem in partial scan desing, and an
optimal solution is found for all the benchmark circuits.
The proveably optimal solutions for the benchmark circuits mainly
use CBILBOs which can simultaneously generate test patterns and
compact test responses. Hence, test scheduling is not required, test
control is simplified, and test application time is reduced.
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| publisher |
IEEE Circuits and Systems Society
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| type |
Text
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| Article in Journal
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| source |
In: IEEE Transactions on Computer-Aided Design of Integrated
Circuits and Systems. Vol. 17(6), pp. 531-539
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| contributor |
Rechnerarchitektur (IFI)
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| subject |
Reliability, Testing, and Fault-Tolerance (CR B.8.1)
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| BILBO
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| built-in self-test
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| CBILBO
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| test register insertion
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